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74LVC595A - 8-bit serial-in/serial-out or parallel-out shift register

General Description

The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Key Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • Overvoltage tolerant inputs to 5.5 V.
  • CMOS low power dissipation.
  • Direct interface with TTL levels.
  • IOFF circuitry provides partial Power-down mode operation.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger action.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).

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Datasheet Details

Part number 74LVC595A
Manufacturer Nexperia
File Size 295.16 KB
Description 8-bit serial-in/serial-out or parallel-out shift register
Datasheet download datasheet 74LVC595A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 3 — 19 November 2021 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.