74LVCH162373A Key Features
- Overvoltage tolerant inputs to 5.5 V
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Multibyte flow-through standard pinout architecture
- Multiple low inductance supply pins for minimum noise and ground bounce
- Direct interface with TTL levels
- All data inputs have bus hold (74LVCH162373A only)
- IOFF circuitry provides partial Power-down mode operation
- plies with JEDEC standard
- JESD8-7A (1.65 V to 1.95 V)
