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74LVCH16373ADGV Datasheet Preview

74LVCH16373ADGV Datasheet

16-bit D-type transparent latch

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74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 9 — 15 February 2019
Product data sheet
1. General description
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate
D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for
bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided
for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V
can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and
5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true outputs.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are
transparent, that is, the latch outputs change each time its corresponding D-input changes. The
latches store the information that was present at the D-inputs one set-up time (tsu) preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at
the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the
OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need
for external pull-up resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A only)
High-impedance when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C




nexperia

74LVCH16373ADGV Datasheet Preview

74LVCH16373ADGV Datasheet

16-bit D-type transparent latch

No Preview Available !

Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74LVC16373ADGG
74LVCH16373ADGG
-40 °C to +125 °C TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
74LVC16373ADL
-40 °C to +125 °C SSOP48
plastic shrink small outline package;
48 leads; body width 7.5 mm
74LVC16373ADGV
74LVCH16373ADGV
-40 °C to +125 °C
TSSOP48 [1] plastic thin shrink small outline package;
48 leads; body width 4.4 mm;
lead pitch 0.4 mm
Version
SOT362-1
SOT370-1
SOT480-1
[1] Also known as TVSOP48.
4. Functional diagram
1
24
1OE 2OE
47
1D0
1Q0
2
46
1D1
1Q1
3
44
1D2
1Q2
5
43
1D3
1Q3
6
41
1D4
1Q4
8
40
1D5
1Q5
9
38
1D6
1Q6 11
37
1D7
1Q7 12
36
2D0
2Q0 13
35
2D1
2Q1 14
33
2D2
2Q2 16
32
2D3
2Q3 17
30
2D4
2Q4 19
29
2D5
2Q5
20
27
2D6
2Q6
22
26
2D7
2Q7
23
1LE 2LE
48
25
Fig. 1. Logic symbol
mgu768
1OE 1 1EN
1LE 48 C3
2OE 24 2EN
2LE 25 C4
1D0 47 3D
1D1 46
1D2 44
1D3 43
1D4 41
1D5 40
1D6 38
1D7 37
2D0 36 4D
2D1 35
2D2 33
2D3 32
2D4 30
2D5 29
2D6 27
2D7 26
Fig. 2. IEC logic symbol
1
2
mgu770
2 1Q0
3 1Q1
5 1Q2
6 1Q3
8 1Q4
9 1Q5
11 1Q6
12 1Q7
13 2Q0
14 2Q1
16 2Q2
17 2Q3
19 2Q4
20 2Q5
22 2Q6
23 2Q7
74LVC_LVCH16373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 February 2019
© Nexperia B.V. 2019. All rights reserved
2 / 17


Part Number 74LVCH16373ADGV
Description 16-bit D-type transparent latch
Maker nexperia
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