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nexperia

74LVCH16374ADGG Datasheet Preview

74LVCH16374ADGG Datasheet

16-bit edge-triggered D-type flip-flop

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74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Rev. 12 — 20 November 2018
Product data sheet
1. General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate
D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus-
oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock
input (nCP) and an output enable (nOE) are provided for each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the
state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to
the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C




nexperia

74LVCH16374ADGG Datasheet Preview

74LVCH16374ADGG Datasheet

16-bit edge-triggered D-type flip-flop

No Preview Available !

Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC16374ADL
-40 °C to +125 °C
74LVC16374ADGG
74LVCH16374ADGG
-40 °C to +125 °C
Name
SSOP48
TSSOP48
Description
plastic shrink small outline package;
48 leads; body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
4. Functional diagram
1
24
1OE 2OE
47 1D0
1Q0 2
46 1D1
1Q1 3
44 1D2
1Q2 5
43 1D3
1Q3 6
41 1D4
1Q4 8
40 1D5
1Q5 9
38 1D6
1Q6 11
37 1D7
1Q7 12
36 2D0
2Q0 13
35 2D1
2Q1 14
33 2D2
2Q2 16
32 2D3
2Q3 17
30 2D4
2Q4 19
29 2D5
2Q5 20
27 2D6
2Q6 22
26 2D7
2Q7 23
1CP 2CP
48
Fig. 1. Logic symbol
25 001aaa253
1OE 1 EN1
1CP 48
C3
2OE 24 EN2
2CP 25
C4
1D0 47 3D
1D1 46
1D2 44
1D3 43
1D4 41
1D5 40
1D6 38
1D7 37
2D0 36 4D
2D1 35
2D2 33
2D3 32
2D4 30
2D5 29
2D6 27
2D7 26
1
2 1Q0
3 1Q1
5 1Q2
6 1Q3
8 1Q4
9 1Q5
11 1Q6
12 1Q7
2
13 2Q0
14 2Q1
16 2Q2
17 2Q3
19 2Q4
20 2Q5
22 2Q6
23 2Q7
001aaa254
Fig. 2. IEC logic symbol
1D0
1CP
1OE
DQ
CP
FF1
1Q0
2D0
2CP
2OE
DQ
2Q0
CP
FF2
Fig. 3. Logic diagram
to 7 other channels
to 7 other channels
001aaa255
74LVC_LVCH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 20 November 2018
© Nexperia B.V. 2018. All rights reserved
2 / 15


Part Number 74LVCH16374ADGG
Description 16-bit edge-triggered D-type flip-flop
Maker nexperia
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