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NPIC6C595-Q100 - Power logic 8-bit shift register

General Description

The NPIC6C595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs.

Both the shift and storage register have separate clocks.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +125 C.
  • Low RDSon.
  • Eight Power EDNMOS transistor outputs of 100 mA continuous current.
  • 250 mA current limit capability.
  • Output clamping voltage 33 V.
  • 30 mJ avalanche energy capability.
  • All registers cleared with single input.
  • Low power consumption.
  • ESD protection:.
  • HBM AEC-Q100-002 revision D exceeds 2500 V.
  • CDM AEC-Q100-011 revision B exc.

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Full PDF Text Transcription for NPIC6C595-Q100 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NPIC6C595-Q100. For precise diagrams, and layout, please refer to the original PDF.

NPIC6C595-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 1 — 12 July 2012 Product data sheet 1. General description The NPIC6C595-Q100 is an 8-bit serial-...

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ta sheet 1. General description The NPIC6C595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR). A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input and to the Q7S output on a LOW-to-HIGH tra

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