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Philips
Philips

74HC195 Datasheet

4-bit parallel access shift register


74HC195 Datasheet Preview


INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT195
4-bit parallel access shift register
Product specification
File under Integrated Circuits, IC06
December 1990
Page 1

Philips Semiconductors
4-bit parallel access shift register
Product specification
74HC/HCT195
FEATURES
Asynchronous master reset
J, K, (D) inputs to the first stage
Fully synchronous serial or parallel data transfer
Shift right and parallel load capability
Complement output from the last stage
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT195 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT195 performs serial, parallel,
serial-to-parallel or parallel-to-serial data transfer at very
high speeds. The “195” operates on two primary modes:
shift right (QoQ1) and parallel load, which are controlled
by the state of the parallel load enable (PE) input. Serial
data enters the first flip-flop (Q0) via the J and K inputs
when the PE input is HIGH and shifted one bit in the
direction Q0 Q1 Q2 Q3 following each
LOW-to-HIGH clock transition. The J and K inputs provide
the flexibility of the JK type input for special applications
and by tying the pins together, the simple D-type input for
general applications. The “195” appears as four common
clocked D flip-flops when the PE input is LOW.
After the LOW-to-HIGH clock transition, data on the
parallel inputs (D0 to D3) is transferred to the respective
Q0 to Q3 outputs. Shift left operation (Q3 Q2) can be
achieved by tying the Qn outputs to the Dn-1 inputs and
holding the PE input LOW.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock transition.
There is no restriction on the activity of the J, K, Dn and
PE inputs for logic operation other than the set-up and
hold time requirements. A LOW on the asynchronous
master reset (MR) input sets all Q outputs LOW,
independent of any other input condition.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1,5 V
TYPICAL
HC
15
57
3.5
105
HCT
15
57
3.5
105
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Page 2

Philips Semiconductors
4-bit parallel access shift register
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7
8
9
10
11
15, 14, 13, 12
16
SYMBOL
MR
J
K
D0 to D3
GND
PE
CP
Q3
Q0 to Q3
VCC
NAME AND FUNCTION
master reset input (active LOW)
first stage J-input (active HIGH)
first stage K-input (active LOW)
parallel data inputs
ground (0 V)
parallel enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
inverted output from the last stage
parallel outputs
positive supply voltage
Product specification
74HC/HCT195
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Page 3
Part Number 74HC195
Manufactur Philips
Description 4-bit parallel access shift register
Total Page 9 Pages
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