HMS30C7202 - Highly-integrated MPU
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Change Log Issue A-01 A-02 A-03 A-04 A-05 A-06 A-07 A-08 Date 2002/08/27 2002/08/28 2002/10/01 2002/10/05 2002/10/14 2002/12/28 2003/01/09 2003/02/26 By Kisun Kim Kisun Kim Kisun Kim Kisun Kim Kisun Kim Kisun Kim Kisun Kim Injae Koo Change The First Draft PMU Freq.
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HMS30C7202 Highly-integrated MPU (ARM Based 32-Bit Microprocessor) Datasheet Version 1.9 ABOV Semiconductor Ltd.
HMS30C7202 HMS30C7202 © 2006 ABOV Semiconductor Ltd.
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- ii - Version 1.9 HMS30C7202 Copyright.
2006 ABOV Semiconductor Ltd.
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HMS30C7202 Features
* 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz 8Kbytes combined instruction/data cache Memory management unit Supports Little Endian operating system 2Kbytes SRAM for internal buffer memory On-chip peripherals with individual power-down: - Multi-channel DMA - 4 Timer Channels with
