S4405 Datasheet - AMCC

S4405 Bicmos PLL Clock Generators

The S4405 BiCMOS clock generators allow the user to generate multiphase TTL clocks in the 10 *80 MHz range with less than 400 ps of skew. Use of a simple off-chip filter allows an entire 160 *320 MHz phaselocked loop (PLL) to be implemented on-chip. Divideby-two and times-two outputs a.

S4405 Features

* Generates six clock outputs from 20 MHz to 80 MHz (HFOUT operates from 10 MHz to 40 MHz)

* Allows PECL or TTL reference input

* Provides differential PECL output at up to 160 MHz

* 21 selectable phase/frequency relationships for the clock outputs

* Compensat

S4405_AMCC.pdf