S5933QE - PCI Interface Device Summary
When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasserts FRAME# on the next clock to indicate the last data phase is in progress. If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to re.
www.DataSheet4U.com PCI Interface Device Summary S5933QE Revision 4 January 6, 1999 Factory Device Update The following are all known device and document errors for the AMCC S5933 PCI Matchmaker revision QE and the 1998 device data book. The workarounds described below are factory suggestions and are not to imply the only or all possible solutions. Contact your local Field Application Engineer for new workaround developements. Also contact your AMCC FAE or local Insight Technical Sales Enginee.
