PLP3 - CMOS Gate Array
PLP3 is a programmable pull-up/pull-down buffer piece.
Logic Symbol Truth Table PLP3 PADM ma mb MA MB PADM Function L L Pull-down HH Pull-up HL Tristate L H Tristate HDL Syntax Verilog PLP3 inst_name (PADM, MA, MB); VHDL inst_name: PLP3 port map (PADM, MA, MB); Power Characteristics
