* Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled a
A67L1618 Datasheet (287.98 KB)
A67L1618
AMIC Technology
287.98 KB
2m x 18- 1m x 36 lvttl pipelined zebl sram.
www.DataSheet4U.com A67L1618/A67L0636 Series Preliminary Document Title 2M X 16, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 0.
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