A48P3616B Datasheet - AMIC

A48P3616B 8M x 16-Bit DDR DRAM

The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR.

A48P3616B Features

* CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5) 133 166 200

* Double data rate architecture: two data transfers per clock cycle.

* Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the

A48P3616B Datasheet (1.45 MB)