Datasheet Details
- Part number
- ATU18
- Manufacturer
- ATMEL
- File Size
- 217.63 KB
- Datasheet
- ATU18_ATMEL.pdf
- Description
- 0.18um ULC
ATU18 Description
www.DataSheet4U.com .ATU18 Features
* High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated PhysicalATU18 Applications
* ATMEL PLL is configurable to support applications as: - Clock tree delay reduction - Zero delay buffer - Phase shift - Frequency synthesis Clock Tree Delay Reduction Typically, clock tree synthesis is able to build a very performant clock tree (for example: 0.15ns of skew for a clock tree connect📁 Related Datasheet
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