Description
The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs.
performance 0.18 um CMOS technology to improve the design frequency and reach 250Mhz typical application and local clock up to 400Mhz.
Features
- High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical synthesis/optimization Flow From 45K Gates up to 1000K Gates Supported From 55Kbit to 847Kbit DPRAM Compatible with Xilinx and Altera Latest FPGA’s Pin-count: Over 700 pins VDD 1.8V +/- 0.15V for core.
ATU18_ATMEL.pdf
