ATU18 Datasheet - ATMEL

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ATU18 0.18um ULC

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The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs.

ATU18_ATMEL.pdf

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Datasheet Details

Part number:

ATU18

Manufacturer:

ATMEL

File Size:

217.63 KB

Description:

0.18um ULC

Features

* High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical

Applications

* ATMEL PLL is configurable to support applications as: - Clock tree delay reduction - Zero delay buffer - Phase shift - Frequency synthesis Clock Tree Delay Reduction Typically, clock tree synthesis is able to build a very performant clock tree (for example: 0.15ns of skew for a clock tree connect

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