A42MX36 - 40MX and 42MX FPGA Families
v5.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 202 User-Programmable I/O Pins 5.6 ns Clock-to-Out 250 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode Commercial, Military Temperature and MIL-STD-88
A42MX36 Features
* such as IEEE Standard 1149.1 (JTAG) Boudary Scan Testing, dual-port SRAM, and fast wide-decode modules. The A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide da
