AX500 - Axcelerator Family FPGAs

Actel

Datasheet Details

Device Architecture 1-1 Programmable Interconnect Element . 1-2 Embedded Memory 1-4 I/O Logic

Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2.
Registered I/Os.
Hot-Swap Compliant I/Os (except PCI).
Programmable Slew Rate and Drive Strength on Outputs.
Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory:.
Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9,.

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