AX500 - Axcelerator Family FPGAs
Device Architecture .
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1-1 Programmable Interconnect Element .
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1-1 Logic Modules .
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v2.7 Axcelerator Family FPGAs u e ™ Leading-Edge Performance 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Up to 2 Million Equivalent System Gates Up to 684 I/Os Up to 10,752 Dedicated Flip-Flops Up to 295 kbits Embedded SRAM/FIFO Manufactured on Advanced 0.15 μm CMOS Antifuse Process Technology, 7 Layers of Metal Single-Chip, Nonvola
AX500 Features
* Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
* Registered I/Os
* Hot-Swap Compliant I/Os (except PCI)
* Programma
