LCK4801 Datasheet - Agere Systems

LCK4801 Low-Voltage HSTL Differential Clock

PCLK0_EN (PULL-UP) PCLK1_EN (PULL-UP) TESTM (PULL-UP) PLLREF_EN (PULL-UP) REF_SEL (PULL-UP) 1 HSTL_CLK (PULL-UP) HSTL_CLK (PULL-UP) PECL_CLK (PULL-UP) PECL_CLK (PULL-UP) (PULL-UP) EXTFB_IN (HSTL) (PULL-DOWN) EXTFB_EN (PULL-UP) EXTFB_OUT (HSTL) SEL[4:0] (PULL-UP) RESET (PULL-UP) PLL_BYPASS (PULL-UP) .

Preliminary Data Sheet July 2001 LCK4801 Low-Voltage HSTL Differential Clock General The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to support single and multiple processor systems that require HSTL differential inputs. The LCK4801 contains a fully integrated PLL (phase-locked loop) which multiplies the HSTL_CLK or PECL_CLK input frequency to match indi.

LCK4801_AgereSystems.pdf