Description
6 Architecture Overview 6 Programmable Logic Cells 7 Programmable Function Unit 8 Look-Up Table Operating Modes 11 Supplemental Logic and Interconnect Cell 21 PLC Latches/Flip-Flops 25 Embedded Block RAM 27 EBR
Features
- s
High-performance platform design.
- 0.13 µm seven-level metal technology.
- Internal performance of >250 MHz (four logic levels).
- I/O performance of >416 MHz for all user I/Os.
- Over 1.5 million usable system gates.
- Meets multiple I/O interface standards.
- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
- Embedded block RAM (EBR) for onboard storage and buffer needs.
- Built-in syste.
OR4-E10.pdf