TLIU04C1 Datasheet - Agere Systems

TLIU04C1 TLIU04C1 Quad T1/E1 Line Interface

8 Microprocessor Mode 8 Overview 8 Pin Information 9 System Interface Pin Options 14 Microprocessor Configuration Modes 14 Microprocessor Interface Pinout Definitions 15 Microprocessor Clock (MPCLK) Specifications 16 Internal Chip Select Function 16 Microprocessor Interface Register Architecture.

TLIU04C1 Features

* s s Transmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. Five pulse equalization settings for template compliance at DSX cross connect. Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder (B8ZS or HDB3). CEPT/E1

TLIU04C1_AgereSystems.pdf