TTSV02622 Datasheet - Agere Systems

TTSV02622 STS-24 Backplane Transceiver

The TTSV02622 can support a 1.24 Gbits/s interface for backplane connections. The 1.24 Gbits/s interface is implemented as dual 622 Mbits/s LVDS links. The HSI macrocell is used for clock/data recovery (CDR) and MUX/deMUX between 77.76 MHz bytewide internal data buses and the 622 Mbits/s external se.

TTSV02622 Features

* s s s s Low-power 3.3 V supply.

* 40 °C to +125 °C industrial temperature range. 272-pin ball grid array (PBGA) package. www.DataSheet4U.com Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. Cl

TTSV02622_AgereSystems.pdf