OR3TP12 - Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Agere Systems

Datasheet Details

Part number	OR3TP12
Manufacturer	Agere Systems
File Size	2.39 MB
Description	Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
Datasheet	OR3TP12_AgereSystems.pdf

7 What Is an FPSC?

include registers for device and subsystem identification and autoconfiguration, support for 64-bit addressing, and multimaster capability that allows any PCI bus Master access to any PCI bus Target. PCI Bus Core Highlights s Implemented in an ORCA Series 3 base array, displacing the bottom four rows of 18 columns. Core is a well-tested ASIC model. Fully compliant to Revision 2.1 of PCI Local Bus Specification (and designed for Revision 2.2). s s.
PCI Local Bus Specification Rev. 2.1, P.

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Published: May 13, 2005 |