TLIU04C1 - TLIU04C1 Quad T1/E1 Line Interface

Agere Systems

TLIU04C1 Datasheet Preview — Preview of TLIU04C1 PDF

Datasheet Details

Part number	TLIU04C1
Manufacturer	Agere Systems
File Size	1.29 MB
Description	TLIU04C1 Quad T1/E1 Line Interface
Datasheet	TLIU04C1_AgereSystems.pdf

TLIU04C1 Product details

Description

8 Microprocessor Mode 8 Overview 8 Pin Information 9 System Interface Pin Options 14 Microprocessor Configuration Modes 14 Microprocessor Interface Pinout Definitions 15 Microprocessor Clock (MPCLK) Specifications 16 Internal Chip Select Function 16 Microprocessor Interface Register Architecture 17 Block Diagrams 18 Data Recovery 20 Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator 20 Receiver Configuration Modes 20 Clock/Data Recovery Mode (CDR) 20 Zero Substitutio

Features

s s Transmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. Five pulse equalization settings for template compliance at DSX cross connect. Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder (B8ZS or HDB3). CEPT/E1 interference immunity as required by G.703. Transmit jitter.

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Published: Apr 16, 2005 |