AS4C128M8D2A Datasheet | Alliance Semiconductor

Features - JEDEC Standard pliant - JEDEC standard 1.8V I/O (SSTL_18-patible) - Power supplies: VDD & VDDQ = +1.8V  0.1V - Operating temperature: TC = 0~85°C (mercial) TC = -40~95°C (Industrial) - Supports JEDEC clock jitter specification - Fully synchronous operation - Fast clock rate: 400 MHz - Differential Clock, CK & CK# - Bidirectional single/differential data strobe - 8 internal banks for concurrent operation - 4-bit prefetch architecture - Internal pipeline architecture - Precharge & active power down - Programmable Mode & Extended Mode registers - Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6 - WRITE latency = READ latency - 1 t CK - Burst lengths: 4 or 8 - Burst type: Sequential / Interleave - DLL enable/disable - Off-Chip Driver (OCD) - Impedance Adjustment - Adjustable data-output drive strength - On-die termination (ODT) - Ro HS pliant - Auto Refresh and Self Refresh - 8192 refresh cycles / 64ms - Average refresh period 7.8s @ -40°C ≦TC≦ +85°C 3.9s @ +85°C ＜TC≦...