AS4C256M16D3LA-12BIN
Features
- JEDEC Standard pliant
- Power supplies: VDD & VDDQ = +1.35V
- Backward patible to VDD & VDDQ = 1.5V ±0.075V
- Operating temperature: -40~95°C (TC)
- Supports JEDEC clock jitter specification
- Fully synchronous operation
- Fast clock rate: 800 MHz
- Differential Clock, CK & CK#
- Bidirectional differential data strobe
- DQS & DQS#
- 8 internal banks for concurrent operation
- 8n-bit prefetch architecture
- Pipelined internal architecture
- Precharge & active power down
- Programmable Mode & Extended Mode registers
- Additive Latency (AL): 0, CL-1, CL-2
- Programmable Burst lengths: 4, 8
- Burst type: Sequential / Interleave
- Output Driver Impedance Control
- 8192 refresh cycles / 64ms
- Average refresh period 7.8 s @ -40°C TC +85°C
3.9 s @ +85°C TC +95°C
- Write Leveling
- ZQ Calibration
- Dynamic ODT (Rtt_Nom & Rtt_WR)
- Ro HS pliant
- Auto Refresh and Self Refresh
- 96-ball 9 x 13 x 1.0mm FBGA package
- Pb and Halogen Free
Overview
The 4Gb Double-Data-Rate-3 (DDR3L)...
