EP2C5 Datasheet - Altera

EP2C5 ISDN Line Interface

www.DataSheet4U.com Section IV. I/O Standards This section provides information on Cyclone™ II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters: Chapter 10, Selectable I/O Standards in Cyclone II Devices Chapter 11, High-Speed Differential Interfaces in Cyclone II Devices Revision History The table below shows the revision history for Chapters 10 and 11. Chapter(s) 10 Date / Version Changes Made November 2004, Upda.

EP2C5 Features

* of systems and devices that operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for a 64-bit bus. The PCI-X 1.0 protocol enhanceme

EP2C5_Altera.pdf