EP610I

EPLD

Altera

EP610I Features

* Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 t

EP610I General Description

The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100% TTL emulation and can easily integrate multiple.

EP610I Datasheet (657.80 KB)

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Datasheet Details

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EP610I

Manufacturer:

Altera

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657.80 KB

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EP610I EPLD Altera

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EP610I Features

EP610I General Description

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