Description
May 1999, ver.5 .
The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration.
Features
* Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900 usable gates (see Table 1)
s Device erasure and reprogramming with non-volatile EPROM configuration elements
s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
s 24 t
Applications
* Classic devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fi