EPM3064A Datasheet - Altera

EPM3064A Programmable Logic

* PCI compatible * Bus *friendly architecture including programmable slew *rate control * Open *drain output option * Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls * Programmable power *saving mode fo.

EPM3064A Features

* High

* performance, low

* cost CMOS EEPROM

* based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)

* 3.3-V in-system programmability (ISP) through the built

* in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pi

EPM3064A Datasheet (729.56 KB)