Description
PCI compatible
Bus
friendly architecture including programmable slew
rate control
Open
drain output option
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power
saving mode for a power reduction of over
50% in each macrocell
Configurable expander product
term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for prote
Features
- High.
- performance, low.
- cost CMOS EEPROM.
- based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1).
- 3.3-V in-system programmability (ISP) through the built.
- in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability.
- ISP circuitry compliant with IEEE Std. 1532.
- Built.
- in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990.
- Enhanced ISP features:.