EPM5128
Features
... s Advanced Multiple Array Matri X (MAX) 5000 architecture bining speed and ease-of-use of PAL devices with the density of programmable gate arrays s plete family of high-performance, erasable CMOS EPROM EPLDs for designs ranging from fast 28-pin address decoders to 100-pin LSI custom peripherals s 600 to 3,750 usable gates (see Table 1) s Fast, 15-ns binatorial delays and 83.3-MHz counter frequencies s Configurable expander product-term distribution allowing more than 32 product terms in a single macrocell s 28 to 100 pins available in DIP, J-lead, PGA, SOIC, and QFP packages s Programmable registers providing D, T, JK, and SR flipflop functionality with individual clear, preset, and clock controls s Programmable security bit for protection of proprietary designs s Software design support featuring Altera’s MAX+PLUS II development system on 486- or Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstations
Table 1. MAX 5000 Device...
