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AD5643R - Dual 12-/14-/16-Bit nanoDAC

Download the AD5643R datasheet PDF. This datasheet also covers the AD5623R variant, as both devices belong to the same dual 12-/14-/16-bit nanodac family and are provided as variant models within a single manufacturer datasheet.

General Description

2.7 V to 5.5 V, dual 16-bit nanoDAC, with external reference GENERAL DESCRIPTION The AD5623R/AD5643R/AD5663R, members of the nanoDAC family, are low power, dual 12-, 14-, and 16-bit buffered voltageout digital-to-analog converters (DAC) that operate from a single 2.7 V to 5.5 V supply and are guara

Key Features

  • Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits AD5643R: 14 bits AD5623R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface up to 50 MHz Hardware LDAC and CLR functions.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AD5623R_AnalogDevices.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Analog Devices

Part Number Description
AD5640 (AD56x0) 12-/14-/16-Bit nanoDAC
AD5641 14-Bit nanoDAC
AD5644R 14-bit nanoDAC
AD5645R nanoDACs
AD5647R Dual 12-/14-/16-Bit nanoDACs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Dual 12-/14-/16-Bit nanoDAC® with 5 ppm/°C On-Chip Reference AD5623R/AD5643R/AD5663R FEATURES Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits AD5643R: 14 bits AD5623R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface up to 50 MHz Hardware LDAC and CLR functions FUNCTIONAL BLOCK DIAGRAM VDD LDAC INPUT REGISTER INTERFACE LOGIC INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB DAC REGISTER STRING DAC A VREFIN /VREFOUT 1.25V/2.