AD8156 Datasheet | Analog Devices

FEATURES 4 × 4, fully differential, nonblocking array Configurable for dual 2 × 2 operation DC to 6.25 Gbps per channel, NRZ data rate Programmable input equalization pensates for over 40” of FR-4 at 6.25 Gbps Multicast and broadcast modes of operation Programmable output swing 100 m V p-p to 1.6 V p-p differential Power supply: 3.3 V (±10%) Low power No EQ: 400 m W typical Maximum EQ: 700 m W typical Inputs: ac-coupled or dc-coupled Wide set of dc-coupled input standards 3.3 V/2.5 V/1.8 V CML or 3.3 V LVPECL Control: LVTTL- or LVCMOS-patible Low additive jitter: 25 ps p-p typical Low random jitter: 0.8 ps rms Integrated 50 Ω termination impedance at inputs/outputs Individual output disable for power savings .. 49-ball, 8 mm × 8 mm BGA, 1 mm pitch FUNCTIONAL BLOCK DIAGRAM INPUT RECEIVERS IN0P/N INPUT EQUALIZATION EQ OUTPUT DRIVERS OUT0P/N IN1P/N IN2P/N 4×4 SWITCH OUT1P/N OUT2P/N IN3P/N OUT3P/N Figure 1. APPLICATIONS Backplane equalization SONET/SDH Gigabit Ethernet XAUI Fibre Channel GENERAL DESCRIPTION The AD8156, a member of the Xstream line of products, is a high speed, fully differential, digital crosspoint switch. The part can function as a 4 × 4 crosspoint switch with double-latched memory, allowing simultaneous updates, or as a dual 2 × 2 with direct output control. The AD8156 has low power dissipation, typically 700 m W on 3.3 V with all outputs and input equalizers active. It operates at any data rate from dc to 6.25 Gbps per port. Each input channel on the AD8156 has a programmable input equalizer to pensate for signal loss over a backplane. The AD8156 high speed inputs are patible with both accoupled and dc-coupled 3.3 V, 2.5 V, or 1.8 V CML, as well as 3.3 V LVPECL data levels. The control interface is LVTTL- and LVCMOS-patible at 3.3 V. All input and output termination resistors are integrated for ease of layout and to minimize impedance mismatch. Input equalization and unused outputs can be individually disabled to minimize...