ADF4151 Datasheet | Analog Devices

FEATURES Fractional-N/Integer-N PLL Synthesizer ADF4151 GENERAL DESCRIPTION The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency. The ADF4151 is used with external VCO parts and is footprint and software patible with the ADF4350. The part consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider [N = (INT + (FRAC/MOD))]. The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4151 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V that can be powered down when not in use. The ADF4151 is available in a 5 mm × 5 mm package. Fractional-N synthesizer and integer-N synthesizer RF bandwidth to 3.5 GHz 3.0 V to 3.6 V power supply 1.8 V logic patibility Separate charge pump supply (VP) allows extended tuning voltage (up to 5.5 V) in 3 V systems Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable RF output phase 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, Wi Max, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM SDVDD AVDDx DVDD VP RSET REFIN ×2 DOUBLER 10-BIT R COUNTER ÷2 DIVIDER LOCK DETECT MULTIPLEXER MUXOUT FLO SWITCH SW LD CLK DATA LE DATA REGISTER FUNCTION LATCH PHASE PARATOR CHARGE...