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National Semiconductor
National Semiconductor

CD4012M Datasheet

Dual 4-Input NOR(NAND) Gate


CD4012M Datasheet Preview


March 1988
CD4002M CD4002C Dual 4-Input NOR Gate
CD4012M CD4012C Dual 4-Input NAND Gate
General Description
These NOR and NAND gates are monolithic complementa-
ry MOS (CMOS) integrated circuits The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swings essentially equal to the supply volt-
age This results in high noise immunity over a wide supply
voltage range No DC power other than that caused by leak-
age current is consumed during static conditions All inputs
are protected against static discharge and latching condi-
tions
Features
Y Wide supply voltage range
Y Low power
Y High noise immunity
3 0V to 15V
10 nW (typ )
0 45 VDD (typ )
Applications
Y Automotive
Y Data terminals
Y Instrumentation
Y Medical Electronics
Y Alarm system
Y Industrial controls
Y Remote metering
Y Computers
Connection Diagrams
CD4002
Dual-In-Line Package
CD4012
Dual-In-Line Package
Top View
TL F 5940 – 1
Order Number CD4002 or CD4012
Top View
TL F 5940 – 2
C1995 National Semiconductor Corporation TL F 5940
RRD-B30M105 Printed in U S A
Page 1

Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
Operating Temperature Range
CD4002M CD4012M
CD4002C CD4012C
VSS b0 3V to VDD a0 3V
b55 C to a125 C
b40 C to a85 C
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
b65 C to a150 C
700 mW
500 mW
Operating Range (VDD)
Lead Temperature (TL)
(Soldering 10 seconds)
VSS a3 0V to VSS a15V
260 C
DC Electrical Characteristics CD4002M CD4012M
Limits
Symbol
Parameter
Conditions
b55 C
a25 C
a125 C Units
Min Max Min Typ Max Min Max
IDD
PD
VOL
VOH
VNL
VNH
IDN
Quiescent
Device Current
Quiescent Device
Dissipation Package
Output Voltage
Low Level
Output Voltage
High Level
Noise Immunity
(All Inputs)
Noise Immunity
(All Inputs)
Output Drive Current
N-Channel (4002)
(Note 2)
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V VI e VDD IO e 0A
VDD e 10V VI e VDD IO e 0A
VDD e 5 0V VI e VSS IO e 0A
VDD e 10V VI e VSS IO e 0A
VDD e 5 0V VO e 3 6V IO e 0A
VDD e 10V VO e 7 2V IO e 0A
VDD e 5 0V VO e 0 95V IO e 0A
VDD e 10V VO e 2 9V IO e 0A
VDD e 5 0V VO e 0 4V VI e VDD
VDD e 10V VO e 0 5V VI e VDD
4 95
9 95
15
30
14
29
05
11
0 05
01
0 25
10
0 05
0 05
4 95
9 95
15
30
15
30
0 40
09
0 001 0 05
0 001 0 1
0 005 0 25
0 01 1 0
0 0 05
0 0 05
50
10
2 25
45
2 25
45
10
25
4 95
9 95
14
29
15
30
0 28
0 65
3 0 mA
6 mA
15 mW
60 mW
0 05 V
0 05 V
V
V
V
V
V
V
mA
mA
IDP Output Drive Current VDD e 5 0V VO e 2 5V VI e VSS b0 62
P-Channel (4002)
VDD e 10V VO e 9 5V VI e VSS b0 62
(Note 2)
b0 5 b2 0
b0 5 b1 0
b0 35
b0 35
mA
mA
IDN Output Drive Current VDD e 5 0V VO e 0 4V VI e VDD 0 31
N-Channel (4012) VDD e 10V VO e 0 5V VI e VDD 0 63
(Note 2)
0 25 0 5
05 06
0 175
0 35
mA
mA
IDP Output Drive Current VDD e 5 0V VO e 2 5V VI e VSS b0 31
P-Channel (4012)
VDD e 10V VO e 9 5V VI e VSS b0 75
(Note 2)
b0 25 b0 5
b0 6 b1 2
b0 175
b0 4
mA
mA
II Input Current
10 pA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 IDN and IDP are tested one output at a time
2
Page 2

DC Electrical Characteristics CD4002C CD4012C
Limits
Symbol
Parameter
Conditions
b55 C
a25 C
a85 C Units
Min Max Min Typ Max Min Max
IDD
PD
VOL
VOH
VNL
VNH
IDN
Quiescent
Device Current
Quiescent Device
Dissipation Package
Output Voltage
Low Level
Output Voltage
High Level
Noise Immunity
(All Inputs)
Noise Immunity
(All Inputs)
Output Drive Current
N-Channel (4002)
(Note 2)
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V VI e VDD IO e 0A
VDD e 10V VI e VDD IO e 0A
VDD e 5 0V VI e VSS IO e 0A
VDD e 10V VI e VSS IO e 0A
VDD e 5 0V VO t 3 6V IO e 0A
VDD e 10V VO t 7 2V IO e 0A
VDD e 5 0V VO s 0 95V IO e 0A
VDD e 10V VO s 2 9V IO e 0A
VDD e 5 0V VO e 0 4V VI e VDD
VDD e 10V VO e 0 5V VI e VDD
4 95
9 95
15
30
14
29
0 35
0 72
05
50
25
50
0 05
0 05
4 95
9 95
15
30
15
30
03
06
0 005 0 5
0 005 5 0
0 025 2 5
0 05 50
0 0 05
0 0 05
50
10
2 25
45
2 25
45
10
25
4 95
9 95
14
29
15
30
0 24
0 48
15
30
75
300
0 05
0 05
mA
mA
mW
mW
V
V
V
V
V
V
V
V
mA
mA
IDN Output Drive Current VDD e 5 0V VO e 0 4V VI e VDD 0 145
N-Channel (4012) VDD e 10V VO e 0 5V VI e VDD 0 3
(Note 2)
0 12 0 5
0 25 0 6
0 095
02
mA
mA
IDP Output Drive Current VDD e 5 0V VO e 2 5V VI e VSS b0 35
P-Channel (4002)
VDD e 10V VO e 9 5V VI e VSS b0 3
(Note 2)
b0 3 b2 0
b0 25 b1 0
b0 24
b0 2
mA
mA
IDP Output Drive Current VDD e 5 0V VO e 2 5V VI e VSS b0 145
P-Channel (4012)
VDD e 10V VO e 9 5V VI e VSS b0 35
(Note 2)
b0 12 b0 5
b0 3 b1 2
b0 095
b0 24
mA
mA
II Input Current
10 pA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 IDN and IDP are tested one output at a time
3
Page 3
Part Number CD4012M
Manufactur National Semiconductor
Description Dual 4-Input NOR(NAND) Gate
Total Page 6 Pages
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