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National Semiconductor
National Semiconductor

CD4042BM Datasheet

Quad Clocked D Latch


CD4042BM Datasheet Preview


March 1988
CD4042BM CD4042BC Quad Clocked D Latch
General Description
The CD4042BM CD4042BC quad clocked ‘‘D’’ latch is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors The outputs Q and Q either latch or follow the
data input depending on the clock level which is pro-
grammed by the polarity input For polarity e 0 the informa-
tion present at the data input is transferred to Q and Q
during 0 clock level and for polarity e 1 the transfer occurs
during the 1 clock level When a clock transition occurs
(positive for polarity e 0 and negative for polarity e 1) the
information present at the input during the clock transition is
retained at the outputs until an opposite clock transition oc-
curs
Features
Y Wide supply voltage range
Y High noise immunity
Y Low power TTL
compatibility
Y Clock polarity control
Y Fully buffered data inputs
Y Q and Q outputs
3 0V to 15V
0 45 VDD (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
Connection Diagram
Dual-In-Line Package
Truth Table
Clock
0
L
1
K
Polarity
0
0
1
1
Q
D
Latch
D
Latch
Order Number CD4042B
Top View
Logic Diagrams
TL F 5966 – 1
TL F 5966 – 2
C1995 National Semiconductor Corporation TL F 5966
TL F 5966 – 4
TL F 5966 – 3
RRD-B30M105 Printed in U S A
Page 1

Absolute Maximum Ratings (Notes 1 and 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
b0 5V to a18V
b0 5V to VDD a0 5V
b65 C to a150 C
700 mW
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions (Note 2)
Supply Voltage (VDD)
3V to 15V
Input Voltage (VIN)
0V to VDD
Operating Temperature Range (TA)
CD4042BM
CD4042BC
b55 C to a125 C
b40 C to a85 C
DC Electrical Characteristics CD4042BM (Note 2)
Symbol
Parameter
Conditions
b55 C
a25 C
a125 C
Units
Min Max Min Typ Max Min Max
IDD Quiescent Device Current VDD e 5V
VDD e 10V
VDD e 15V
1 0 02 1 30 mA
2 0 02 2 60 mA
4
0 02 4
120 mA
l lVOL Low Level Output Voltage IO k 1 mA VIH e VDD VIL e 0V
VDD e 5V
VDD e 10V
VDD e 15V
0 05
0 05
0 05
0 0 05
0 0 05
0 0 05
0 05 V
0 05 V
0 05 V
VOH
l lHigh Level Output Voltage IO k 1 mA VIH e VDD VIL e 0V
VDD e 5V
VDD e 10V
VDD e 15V
4 95
9 95
14 95
4 95
9 95
14 95
5
10
15
4 95
9 95
14 95
V
V
V
l lVIL Low Level Input Voltage IO k 1 mA
VDD e 5V VO e 0 5V or 4 5V
15
2 25 1 5
15 V
VDD e 10V VO e 1V or 9V
30
45 30
30 V
VDD e 15V VO e 1 5V or 13 5V
40
6 75 4 0
40 V
l lVIH High Level Input Voltage IO k 1 mA
VDD e 5V VO e 0 5V or 4 5V
35
VDD e 10V VO e 1V or 9V
70
VDD e 15V VO e 1 5V or 13 5V 11 0
3 5 2 75
70 55
11 0 8 25
35
70
11 0
V
V
V
IOL Low Level Output Current VIH e VDD VIL e 0V
(Note 4)
VDD e 5V VO e 0 4V
VDD e 10V VO e 0 5V
VDD e 15V VO e 1 5V
0 64 0 51 0 88
1 6 1 3 2 25
42 34 88
0 36 mA
0 9 mA
2 4 mA
IOH High Level Output Current VIH e VDD VIL e 0V
(Note 4)
VDD e5V VO e 4 6V
VDD e10V VO e 9 5V
VDD e15V VO e 13 5V
b0 64
b1 6
b4 2
b0 51 b0 88
b1 3 b2 25
b3 4 b8 8
b0 36
b0 9
b2 4
mA
mA
mA
IIN Input Curent
VDD e 15V VIN e 0V
VDD e 15V VIN e 15V
b0 1
01
b10b5 b0 1
10b5 0 1
b1 0 mA
1 0 mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 VSS e 0V unless otherwise specified
Note 3 Being a latch the CD4042BM CD4042BC is not clock rise and fall time sensitive
Note 4 IOH and IOL are tested one output at a time
2
Page 2

DC Electrical Characteristics CD4042BC (Note 2)
Symbol
Parameter
Conditions
b40 C
a25 C
a85 C
Units
Min Max Min Typ Max Min Max
IDD Quiescent Device Current VDD e 5V
VDD e 10V
VDD e 15V
4 0 02 4 30 mA
8 0 02 8 60 mA
16
0 02 16
120 mA
l lVOL Low Level Output Voltage IO k 1 mA VIH e VDD VIL e 0V
VDD e 5V
VDD e 10V
VDD e 15V
0 05
0 05
0 05
0 0 05
0 0 05
0 0 05
0 05 V
0 05 V
0 05 V
VOH
l lHigh Level Output Voltage IO k 1 mA VIH e VDD VIL e 0V
VDD e 5V
VDD e 10V
VDD e 15V
4 95
9 95
14 95
4 95
9 95
14 95
5
10
15
4 95
9 95
14 95
V
V
V
l lVIL Low Level Input Voltage IO k 1 mA
VDD e 5V VO e 0 5V or 4 5V
15
2 25 1 5
15 V
VDD e 10V VO e 1V or 9V
30
45 30
30 V
VDD e 15V VO e 1 5V or 13 5V
40
6 75 4 0
40 V
l lVIH High Level Input Voltage IO k 1 mA
VDD e 5V VO e 0 5V or 4 5V
35
VDD e 10V VO e 1V or 9V
70
VDD e 15V VO e 1 5V or 13 5V 11 0
3 5 2 75
70 55
11 0 8 25
35
70
11 0
V
V
V
IOL Low Level Output Current VIH e VDD VIL e 0V
(Note 4)
VDD e 5V VO e 0 4V
VDD e 10V VO e 0 5V
VDD e 15V VO e 1 5V
0 52 0 44 0 88
1 3 1 1 2 25
36 30 88
0 36 mA
0 9 mA
2 4 mA
IOH High Level Output Current VIH e VDD VIL e 0V
(Note 4)
VDD e5V VO e 4 6V
VDD e 10V VO e 9 5V
VDD e15V VO e 13 5V
b0 52
b1 3
b3 6
b0 44 b0 88
b1 1 b2 25
b3 0 b8 8
b0 36
b0 9
b2 4
mA
mA
mA
IIN Input Curent
VDD e 15V VIN e 0V
VDD e 15V VIN e 15V
b0 3
03
b10b5 b0 3
10b5 0 3
b1 0 mA
1 0 mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 VSS e 0V unless otherwise specified
Note 3 Being a latch the CD4042BM CD4042BC is not clock rise and fall time sensitive
Note 4 IOH and IOL are tested one output at a time
3
Page 3
Part Number CD4042BM
Manufactur National Semiconductor
Description Quad Clocked D Latch
Total Page 6 Pages
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