NE33200 Datasheet - California Eastern

NE33200 SUPER LOW NOISE HJ FET

The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create a two-dimensional electron gas layer with very high electron mobility. Its excellent low noise figure and high associated gain make it suitable for commercial and industrial appl.

NE33200 Features

* VERY LOW NOISE FIGURE: 0.75 dB typical at 12 GHz Optimum Noise Figure, NFOPT (dB) 4 3.5 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA 24 21 18 15 12 9 6 NF 0.5 0 1 10 30 3 0

* HIGH ASSOCIATED GAIN: 10.5 dB Typical at 12 GHz

* GATE LENGTH: 0.3 µm

NE33200-CaliforniaEastern.pdf