CY14B512Q1 Datasheet - Cypress Semiconductor

CY14B512Q1 512-Kbit (64 K X 8) Serial (SPI) nvSRAM

9 Status Register 10 Read Status Register (RDSR) Instruction 10 Write Status Register (WRSR) Instruction 10 Write Protection and Block Protection 11 Write Enable (WREN) Instruction 11 Write Disable (WRDI) Instruction 11 Block Protection 11 Write Protect (WP) Pin 12 Memory Access 12 Read Seque.

CY14B512Q1 Features

* 512-Kbit nonvolatile static random access memory (nvSRAM)

* Internally organized as 64 K × 8

* STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE)

* RECALL

CY14B512Q1_CypressSemiconductor.pdf