CY14B512Q1
Features
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512-Kbit nonvolatile static random access memory (nv SRAM)
- Internally organized as 64 K × 8
- STORE to Quantum Trap nonvolatile elements initiated automatically on power-down (Auto Store) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE)
- RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
- Automatic STORE on power-down with a small capacitor (except for CY14B512Q1) High reliability
- Infinite read, write, and RECALL cycles
- 1 million STORE cycles to Quantum Trap
- Data retention: 20 years High speed serial peripheral interface (SPI)
- 40 MHz clock rate
- Supports SPI mode 0 (0,0) and mode 3 (1,1) Write protection
- Hardware protection using Write Protect (WP) pin
- Software protection using Write Disable instruction
- Software block protection for 1/4,1/2, or entire array Low power consumption
- Single 3 V +20%,
- 10% operation
- Average active current of 10 m A at 40 MHz operation
Industry standard...
