CY14MB064J Datasheet - Cypress Semiconductor

CY14MB064J 64-Kbit (8 K x 8) Serial (I2C) nvSRAM

Clock. Runs at speeds up to a maximum of fSCL. I/O. Input/Output of data through I2C interface. Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be left open if not connected. Slave Address. Defines the slave address for I2C. This pin is internally .

CY14MB064J Features

* 64-Kbit nonvolatile static random access memory (nvSRAM)

* Internally organized as 8 K × 8

* STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)

* RECALL to SRAM initiated on powe

CY14MB064J_CypressSemiconductor.pdf