Description
The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance.
Features
- In-System Reprogrammable™ (ISR™) CMOS CPLDs.
- JTAG interface for reconfigurability.
- Design changes do not cause pinout changes.
- Design changes do not cause timing changes.
- High density.
- 32 to 512 macrocells.
- 32 to 264 I/O pins.
- Five dedicated inputs including four clock pins.
- Simple timing model.
- No fanout delays.
- No expander delays.
- No dedicated vs. I/O pin delays.
- No additional.
