Description
1 7C09579V: 10/97 Revision: May 1, 2000 .
The CY7C09569V and CY7C09579V are high-speed 3.
Features
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* True dual-ported memory cells which allow simultaneous access of the same memory location
* Two Flow-Through/Pipelined devices
* 16K x 36 organization (CY7C09569V)
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PRELIMINARY
CY7C09569V CY7C09579V
3.3V 16K/32K x 36 FLEx36™
Applications
* A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTE
