CY7C1024DV33 Datasheet | Cypress

3-Mbit (128 K × 24) Static RAM Features I Highspeed Ë t AA = 10 ns I Low activepower Ë ICC = 175 m A at f= 100 MHz I Low CMOS standbypower Ë ISB2 = 25 m A I Operatingvoltages of3.3 ±0.3 V I 2.0 V data retention I Automatic power-downwhendeselected I Transistor-transistorlogic (TTL) patibleinputs andoutputs I Easymemoryexpansionwith CE1, CE2, and CE3 Features I Availablein Pb-freestandard119-ball PBGA Functional Description The CY7C1024DV33 is a highperformance CMOS static RAM organizedas 128 K words by24 bits. This devicehas an automatic power-downfeaturethat significantlyreduces power consum ption when deselected. Towritetothedevice, enablethechip(CE1 LOW, CE2 HIGH, and CE3 LOW), whileforcingthe Write Enable(WE) input LOW. Toreadfrom thedevice, enablethechipbytaking CE1 LOW, CE2 HIGH, and CE3 LOW whileforcingthe Output Enable(OE) LOW andthe Write Enable(WE) HIGH. Seethe Truth Tableonpage 7 fora pletedescriptionof Readand Writemodes. The24 I/O pins (I/O0 to I/O23) areplacedina highimpedance statewhenthedeviceis deselected(CE1 HIGH, CE2 LOW, or CE3 HIGH) orwhentheoutput enable(OE) is HIGH duringa writeoperation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW). Logic Block Diagram INPUT BUFFER A(9:0) 128K x24 ARRAY I/O0 - I/O23 ROW DECODER SENSE AMPS COLUMN DECODER A(16:10) CONTROL LOGIC CE1, CE2, CE3 WE OE Cypress Sem iconductor Corporation - 198 Champion Court Document Number:001-08353 Rev. - E - San Jose, CA...