CY7C1410JV18
Features
- Configurations
- 4M x 8 CY7C1425JV18
- 4M x 9 CY7C1412JV18
- 2M x 18 CY7C1414JV18
- 1M x 36
Separate independent read and write data ports
- Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534 MHz) at 267 MHz
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- Double Data Rate (DDR) interfaces on both read and write ports ..
- Functional Description
The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon IO devices. Access to each port is acplished through a mon address bus. The read...
