CY7C1410V18
Features
- Separate Independent Read and Write data ports
- Supports concurrent transactions
- 200-MHz clock for high bandwidth
- 2-Word Burst on all accesses
- Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz ..
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two output clocks (C and C) accounts for clock skew and flight time mismatching
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Single multiplexed address input bus latches address inputs for both Read and Write ports
- Separate Port Selects for depth expansion
- Synchronous internally self-timed writes
- Available in x8, x9, x18, and x36 configurations
- Full data coherency, providing most current data
- Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
- 15 × 17 × 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix)
- Variable drive HSTL output buffers
- JTAG 1149.1 patible test access port
- Delay Lock Loop...
