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CY7C1410V18 Datasheet (CY7C14xxV18) SRAM 2-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Download the CY7C1410V18 datasheet PDF. This datasheet also includes the CY7C1412V18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1412V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

The CY7C1410V18, CY7C1425V18, CY7C1412V18, and CY7C1414V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

Overview

PRELIMINARY CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 36-Mbit QDR-II™ SRAM 2-Word Burst.

Key Features

  • Separate Independent Read and Write data ports.
  • Supports concurrent transactions.
  • 200-MHz clock for high bandwidth.
  • 2-Word Burst on all accesses.
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz www. DataSheet4U. com.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) accounts for clock skew and flight time mismatchi.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1410AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C141 1K x 8 Dual-Port Static RAM
CY7C1411AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18 (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18 (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411KV18 36-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1412AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412JV18 SRAM 2-Word Burst Architecture
CY7C1412KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture