S26KS512S, S26KL512S Datasheet - Cypress Semiconductor

S26KS512S - high-speed CMOS MirrorBit NOR flash devices

4 1.1 DDR Center Aligned Read Strobe Functionality (DCARS) 6 1.2 Error Detection and Correction Functionality 6 2. Connection Diagram 9 2.1 FBGA 24-Ball 5 x 5 Array Footprint 9 3. Signal Description 10 4. HyperBus Protocol 11 4.1 Command / Address Bit Assignments 11 4.2 Read Operations 12 4.3 .

S26KS512S Features

* 3.0V I/O, 11 bus signals

* Single ended clock

* 1.8V I/O, 12 bus signals

* Differential clock (CK, CK#)

* Chip Select (CS#)

* 8-bit data bus (DQ[7:0])

* Read-Write Data Strobe (RWDS)

* HyperFlash™ memories use RWDS only as a Read Data Strobe

* Up to 333 MBps sus

S26KL512S-CypressSemiconductor.pdf