Description
4 1.1 DDR Center Aligned Read Strobe
Functionality (.
Features
- 3.0V I/O, 11 bus signals.
- Single ended clock.
- 1.8V I/O, 12 bus signals.
- Differential clock (CK, CK#).
- Chip Select (CS#).
- 8-bit data bus (DQ[7:0]).
- Read-Write Data Strobe (RWDS).
- HyperFlashâ„¢ memories use RWDS only as a Read Data Strobe.
- Up to 333 MBps sustained read throughput.
- DDR.
- two data transfers per clock.
- 166-MHz clock rate (333 MBps) at 1.8V VCC.
- 100-MHz clock rate (200 MBps) at 3.0V VCC.
- 96-ns initial random read.