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CY7C1462SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM

This page provides the datasheet information for the CY7C1462SV25, a member of the CY7C1460SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM family.

Datasheet Summary

Description

The CY7C1460SV25/CY7C1462SV25 are 2.5 V, 1M × 36/2M × 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively.

They are designed to support unlimited true back to back Read/Write operations with no wait states.

Features

  • Pin compatible and functionally equivalent to ZBT™.
  • Supports 250-MHz bus operations with zero wait states.
  • Available speed grades are 250 and 167 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte Write capability.
  • 2.5-V core power supply.
  • 2.5-V I/O power supply.
  • Fast clock-to-output times.
  • 2.6 ns (for 250-MHz device).
  • Clock Enabl.

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Datasheet preview – CY7C1462SV25

Datasheet Details

Part number CY7C1462SV25
Manufacturer Cypress
File Size 351.51 KB
Description 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
Datasheet download datasheet CY7C1462SV25 Datasheet
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Full PDF Text Transcription

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CY7C1460SV25 CY7C1462SV25 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades are 250 and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte Write capability ■ 2.5-V core power supply ■ 2.5-V I/O power supply ■ Fast clock-to-output times ❐ 2.6 ns (for 250-MHz device) ■ Clock Enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ CY7C1460SV25 available in JEDEC-standard Pb-free 100-pin TQFP package and non Pb-free 165-ball FBGA package.
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