CY7C1462SV25
Features
- Pin patible and functionally equivalent to ZBT™
- Supports 250-MHz bus operations with zero wait states
- Available speed grades are 250 and 167 MHz
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte Write capability
- 2.5-V core power supply
- 2.5-V I/O power supply
- Fast clock-to-output times
- 2.6 ns (for 250-MHz device)
- Clock Enable (CEN) pin to suspend operation
- Synchronous self-timed writes
- CY7C1460SV25 available in JEDEC-standard Pb-free 100-pin
TQFP package and non Pb-free 165-ball FBGA package. CY7C1462SV25 available in Pb-free 100-pin TQFP package
- IEEE 1149.1 JTAG-patible Boundary Scan
- Burst capability
- linear or interleaved burst order
- “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460SV25/CY7C1462SV25 are 2.5 V, 1M × 36/2M × 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (No BL logic,...
