P2V64S40ETP Datasheet - Deutron Electronics

P2V64S40ETP 64Mb Synchronous DRAM

The P2V64S40ETP is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst .

P2V64S40ETP Features

* 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) Pin Configurations

* All inputs a

P2V64S40ETP Datasheet (676.03 KB)