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M14D5121632A-2.5BG2A

DDR-II SDRAM

M14D5121632A-2.5BG2A Features

* JEDEC Standard

* VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V

* Internal pipelined double-data-rate architecture; two data access per clock cycle

* Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

* On-chip DLL

* Diff

M14D5121632A-2.5BG2A General Description

Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Command input Command input Command input Ground Power Pin Na.

M14D5121632A-2.5BG2A Datasheet (2.04 MB)

Preview of M14D5121632A-2.5BG2A PDF

Datasheet Details

Part number:

M14D5121632A-2.5BG2A

Manufacturer:

ESMT

File Size:

2.04 MB

Description:

Ddr-ii sdram.

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M14D5121632A-2.5BG2A DDR-II SDRAM ESMT

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