PST3324 Datasheet - ETC

PST3324 CMOS System Reset

of Operation (1) VDD > VS, VOUT: H (M1: ON, M2, M3: OFF) When VDD is gradually lowered from the above state, detection voltage is as follows. Detection voltage: (R1 + R2 + R3) / (R2 + R3) VREF (2) VDD < VS, VOUT: L (M1: OFF, M2, M3: ON) When VDD is gradually raised from the above state, release vol.

PST3324 Features

* (1) Super low consumption current (2) High precision detection voltage (3) Hysteresis characteristic (4) Operating range (5) Wide operating temperature range (6) Detection voltage 0.25µA typ. (when VDD = Vs + 1V) ±2% 5% typ. 0.95 ~ 10V -30 ~ +85°C 2 ~ 6V (0.1V step) Package SC-82AB (PST31XX, PST32X

PST3324 Datasheet (177.66 KB)