TM50S116T Datasheet - ETC

TM50S116T SDRAM

TM50S116T SDRAM The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16), fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro.

TM50S116T Features

* n Package 400-mil 50-pin TSOP(II) n JEDEC PC133/PC100 compatible n Single 3.3V Power Supply n LVTTL Signal Compatible n Byte control(DQML and DQMU) n Auto and Self Refresh n 64ms refresh period (4K cycles) n 11-Row x 8-Column organization n 2-Bank operation controlled by BA0 n Programmable n Pin33 a

TM50S116T_ETC.pdf