* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
E5108AGBG Datasheet (674.27 KB)
E5108AGBG
Elpida Memory
674.27 KB
ede5108agbg.
DATA SHEET
512M bits DDR2 SDRAM
EDE5108AGBG (64M words × 8 bits)
Specifications
* Density: 512M bits
* Organization ⎯ 16M words × 8 b.
📁 Related Datasheet
E5108ASE - EDE5108ASE
(Elpida Memory)
PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AGSE (128M words × 4 bits) EDE5108AGSE (64M words × 8 bits)
Description
The EDE5104AGSE is a 512M .
E500 - current regulator diodes
(Siliconix)
current regulator diodes
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designed for. • •
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E501 - current regulator diodes
(Siliconix)
current regulator diodes
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designed for. • •
Current Regulation
• Current Limiting • Biasing •• Linear Ramp and Staircase
Generator
Perfor.
E502 - current regulator diodes
(Siliconix)
current regulator diodes
H
m
«ooII
designed for. • •
Current Regulation
• Current Limiting • Biasing •• Linear Ramp and Staircase
Generator
Perfor.
E503 - current regulator diodes
(Siliconix)
current regulator diodes
H
m
«ooII
designed for. • •
Current Regulation
• Current Limiting • Biasing •• Linear Ramp and Staircase
Generator
Perfor.
E504 - current regulator diodes
(Siliconix)
current regulator diodes
H
m
«ooII
designed for. • •
Current Regulation
• Current Limiting • Biasing •• Linear Ramp and Staircase
Generator
Perfor.
E505 - current regulator diodes
(Siliconix)
current regulator diodes
H
m
«ooII
designed for. • •
Current Regulation
• Current Limiting • Biasing •• Linear Ramp and Staircase
Generator
Perfor.
E506 - current regulator diodes
(Siliconix)
current regulator diodes
H
m
«ooII
designed for. • •
Current Regulation
• Current Limiting • Biasing •• Linear Ramp and Staircase
Generator
Perfor.
