* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE11UD8AGUA Datasheet (235.52 KB)
EBE11UD8AGUA
Elpida Memory
235.52 KB
1gb ddr2 sdram so-dimm.
DATA SHEET www.DataSheet4U.com 1GB DDR2 SDRAM SO-DIMM EBE11UD8AGUA (128M words × 64 bits, 2 Ranks) Specifications Density: 1GB O.
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