* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE20AE4ACWA Datasheet (268.29 KB)
EBE20AE4ACWA
Elpida Memory
268.29 KB
2gb registered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 2GB Registered DDR2 SDRAM DIMM EBE20AE4ACWA (256M words × 72 bits, 1 Rank) Specifications Density: 2GB
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