* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE82AF4A1RA Datasheet (287.63 KB)
EBE82AF4A1RA
Elpida Memory
287.63 KB
8gb registered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 8GB Registered DDR2 SDRAM DIMM EBE82AF4A1RA (1024M words × 72 bits, 4 Ranks) Specifications Den.
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